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Note that for simple graphs, no Figure 15.11 A graph and its incidence matrix matter how many vertices and edges they have, there will always be exactly two 1s in each column of any incidence matrix. Why (See Review Question 15.9 on page 305.) THE ADJACENCY LIST FOR A GRAPH An adjacency list (or adjacency structure) for a graph (V, E) is a list that contains one element for each vertex in the graph and in which each vertex list element contains a list of the vertices that are adjacent to its vertex. The secondary list for each vertex is called its edge list. EXAMPLE 15.12 An Adjacency List

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In day-to-day work with databases, one is less likely to focus on these higher forms, so this chapter will end its discussion of normalization with BCNF The important guide to remember is that each relation should embrace a single theme, a single topic SQL STRUCTURED QUERY LANGUAGE IBM first brought SQL to database processing It is a high-level language for creating databases, manipulating data, and retrieving sets of data SQL is a nonprocedural language that is, SQL statements describe the data and operations of interest, but do not specify in detail how the underlying database system is to satisfy the request..

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Figure 15.12 shows the adjacency list for the graph in Figure 15.1 on page 285. The edge list for vertex a has three elements, one for each of the three edges that are incident with a; the edge list for vertex b has two elements, one for each of the two edges that are incident with b; and so on.

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Note that each edge list element corresponds to a unique 1 entry in the graph s corresponding incidence matrix. For example, the three elements in the edge list for vertex a correspond to the three 1s in the first row (the row for vertex a) in the incidence matrix in Figure 15.11.

ANSI standards for SQL were published in 1986, 1989, 1992, 1999, and 2003 In practice, different database vendors offer SQL with small differences in syntax and semantics For any particular vendor, most SQL statements will conform to the standard, and there will also be numerous small differences As a result, one must always supplement knowledge of standard SQL with information specific to the database vendor one is using The desktop reference SQL in a Nutshell by Kevin Kline (2004) finds it necessary, for example, to include separate sections for ANSI Standard, DB2 (IBM), MySQL (open source), Oracle, and SQL Server (Microsoft) varieties of the standard SQL statements are often distinguished as being part of the data definition language (DDL) or the data manipulation language (DML) DDL statements create database structures like tables, views, triggers, and procedures DML statements insert data, update data, retrieve data, or delete data in the database.

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Also note that the edge lists are not ordered, that is, their order is irrelevant. DIGRAPHS A digraph (or directed graph) is a pair G = (V, E) where V is a finite set and E is a set of ordered pairs of elements of V. As with (undirected) graphs, the elements of V are called vertices (or nodes) and the elements of E are called edges (or arcs). If e E, then e = (a, b) for some a, b V. In this case, we can denote e more simply as e = ab. We say that the edge e emanates from (or is incident from) vertex a and terminates at (or is incident to) vertex b. The outdegree of a vertex is the number of edges that emanate from it. The indegree of a vertex is the number of edges that terminate at it. Note that, unlike the graph definition, the digraph definition naturally allows an edge to terminate at the same vertex from which it emanates. Such an edge is called a loop. A simple digraph is a digraph that has no loops. EXAMPLE 15.13 A Digraph Figure 15.13 shows a digraph with vertex set V = {a, b, c, d} and edge set E = {ab, ad, bd, ca, dc}. Vertex a has outdegree 2 and indegree 1. Vertices b and c each have outdegree 1 and indegree 1. Vertex d has outdegree 1 and indegree 2.

Fig. 2-25 i.e., the diode voltages have the same ordering as the input voltages. Suppose that v1 is positive and exceeds v2 and v3 . Then D1 must be forward-biased, with vD1 0 and, consequently, vD2 < 0 and vD3 < 0. Hence, D2 and D3 block, while v1 is passed as vo . This is so in general: The logic of the OR gate is that the largest positive input signal is passed as vo , while the remainder of the input signals are blocked. If all input signals are negative, vo 0. Application of this logic gives the sketch of vo in Fig. 2-25(c).