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Theorem. Every subtree of an AVL tree is an AVL tree. Proof: The proof that every subtree of a binary search tree is a binary search tree is given in Problem 12.6. If a S is a subtree of an AVL tree T, then every node is S is also in T. Therefore, the balance number at every node in S is 1, 0, or 1.

Is this schema in 1NF yes Is this schema in 2NF No, aside from attributes Description and Price, none of the attributes of the Sales table is functionally dependent on the key Item_ID. Is this schema in 3NF No, several transitive dependencies exist; for instance, Addr, City, St, ZIP, and Phone are dependent upon Customer_Name. If the answer to any of these questions is, No, redesign the table so that the result is in 3NF. Sales Item_ID | Description | Price | Date | Customer_Name

The logic AND gate of Fig. 2-46(a) is to be used to generate a crude pulse train by letting v1 10 sin !t V and v2 5 V. Determine (a) the amplitude and (b) the period of the pulse train appearing as vo . Ans: a 5 V; b 2 =! In the circuit of Fig. 2-29, vS is a 10-V square wave with a 4-ms period. The diode is nonideal, with the characteristic of Fig. 2-26(b). If the capacitor is initially uncharged, determine vC for the rst cycle of vs . Ans: 9:5 1 e 333:3t V for 0 t < 2 ms and 4.62 V for 2 t < 4 ms The forward voltage across the diode of Problem 2.35 is vD 0:3 0:060 cos t V. Find the ac component of the diode current id . Ans: 2:52 cos t mA The circuit of Fig. 2-47(a) is a voltage-doubler circuit, sometimes used as a low-level power supply when the load RL is reasonably constant. It is called a doubler because the steady-state peak value of vL is twice the peak value of the sinusoidal source voltage. Figure 2-47(b) is a sketch of the steady-state output voltage for vs 10 cos !t V. Assume ideal diodes, ! 120 rad/s, C1 20 F, C2 100 F, and RL 20 k . (a) Solve by SPICE methods for the decay time td . (b) From the SPICE results, determine the peak-topeak value of the ripple voltage. (Netlist code available from author website.) Ans: a 15:52 ms; (b) 0.75 V

HEAPS A heap is a complete binary tree whose elements have keys that satisfy the following heap property: the keys along any path from root to leaf are descending (i.e., nonincreasing). EXAMPLE 13.1 A Heap

D2 _ 0 (a)

8.4 Two of the tables in the antique store database will be a table of Deliveries, and a table of Delivery_Services. Here are the schemas for the two tables: Deliveries Date/Time | Customer_ID | Delivery_Service | Cost | Invoice_No | Driver Delivery_Services Name | Phone | Addr | City | St | ZIP | Contact Write the SQL code to create these tables. Specify which columns may not be NULL, and specify primary and foreign key constraints. Note that the Delivery_Service column in the Deliveries table is meant to have the same meaning as the Name column in the Delivery_Service table. CREATE TABLE DELIVERIES ( DATETIME TIMESTAMP NOT NULL, CUSTOMER_ID INT NOT NULL, DELIVERY_SERVICE VARCHAR(20) NOT NULL, COST NUMERIC(8,2), NOT NULL INVOICE_NO CHAR(8) NOT NULL, DRIVER VARCHAR(20), PRIMARY KEY(DATETIME, CUSTOMER_ID), FOREIGN KEY(DELIVERY_SERVICE) REFERENCES DELIVERY_SERVICES(NAME) ); CREATE TABLE DELIVERY_SERVICES( NAME VARCHAR(20) NOT PHONE CHAR(12) NOT ADDR VARCHAR(30) NOT ST CHAR(2) NOT ZIP CHAR(5) NOT CONTACT VARCHAR(20), PRIMARY KEY(NAME) );

Fig. 2-47

Figure 13.1 shows a heap. Note that the keys along each of its root-to-leaf paths are descending: 77 66 44 22; 77 66 44 41; 77 66 60 58; 77 66 60 25; 77 55 33 29; 77 55 55.

Find the diode current during one capacitor-charging cycle in the recti er circuit of Fig 2-15(a) if C 47 F; RL 1 k ; and vS 90 cos 2000t V (Hint: The approximate ripple formula cannot be used, as it implicitly assumes zero capacitor charging time Instead, solve for capacitor current and load current, and add) Ans: iD 8:49 sin 2000t 0:68 A for 2:966 ms t < 3:142 ms In the circuit of Fig 2-32, R1 RL 10 If the diode is ideal and vS 10 sin !t V, nd the average value of the load voltage vL Ans: 3:18 V Rework Problem 220 with the diode of Fig 2-18(b) reversed and all else unchanged (The circuit is now a positive clamping circuit.

15.19 15.20